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Question #159inputverified

The given circuit shows an implementation of a BSPD latch. Evaluate the time to trigger: transition of both inputs from Vs to 0V. State the results in milliseconds. Round to one decimal place. Evaluate the time to reset: transition of both inputs from 0V to Vs. State the results in seconds. Round to one decimal place. The following conditions are assumed: Vs = 5V R1 = 68kΩ R2 = 2.2MΩ C1 = 3.3μF ideal Diodes with constant Vf = 0.7V and Ir = 0A FETs as ideal "switches" with Vth somewhere between 1V and 4V, Rds_on = 0Ω and Ices = 0A ideal operational amplifier at least on trigger and reset cycle already occurred before the circuit has reached steady state before the input transition there is an input conditioning circuit evaluating hard braking and respective power delivery or throttle position with digital outputs which is not shown in the schematic both digital inputs have always exactly the same logical state which is either 0V, trigger conditition, or Vs, idle Give your answer in the following format: time to trigger, time to reset. Example: if the time to trigger is 1234,5ms and the time to reset is 12,3s then use 1234.5, 12.3 as answer value.

Electrical latch schematic. A supply V_s at upper left feeds resistor R1 and a node connected to the drains of two grounded transistors T1 and T2, whose control inputs are labelled 'Power' and 'Brake'; each input has a 10 kΩ pull-down resistor. Two right-facing diodes D1 and D2 run in series from this node toward resistor R2 and output 'Out'. The node between D1 and D2 connects to capacitor C1 to ground and to the − input of an op-amp/comparator. The + input is connected to the midpoint of two vertical 100 kΩ resistors between Out and a lower bias node; that bias node lies between two 10 kΩ resistors connected to V_s and ground. Comparator output joins Out. Small 'Trig'/'OK' timing step drawings appear near the input and output, and an output-driven element plus an SDC contact are drawn on the right.
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Electrical latch schematic. A supply V_s at upper left feeds resistor R1 and a node connected to the drains of two grounded transistors T1 and T2, whose control inputs are labelled 'Power' and 'Brake'; each input has a 10 kΩ pull-down resistor. Two right-facing diodes D1 and D2 run in series from this node toward resistor R2 and output 'Out'. The node between D1 and D2 connects to capacitor C1 to ground and to the − input of an op-amp/comparator. The + input is connected to the midpoint of two vertical 100 kΩ resistors between Out and a lower bias node; that bias node lies between two 10 kΩ resistors connected to V_s and ground. Comparator output joins Out. Small 'Trig'/'OK' timing step drawings appear near the input and output, and an output-driven element plus an SDC contact are drawn on the right.

  1. 399.4, 13.8Correct

Official answer

399.4, 13.8

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  • FSG 2021 · ev · quiz 16